Ferroelectric Analog Non-Volatile Memory

• FA-NVM is a non-volatile memory technology that uses partial ferroelectric polarization switching to achieve stable, multi-level analog storage.
• Architectures like FTJ, FeFET, and memcapacitors, utilizing materials such as HZO, AlScN, and CIPS, deliver high density, endurance, and energy efficiency.
• Advanced programming schemes and device integration enable precise analog state control, supporting applications in in-memory computing and neuromorphic systems.

Ferroelectric analog non-volatile memory (FA-NVM) is a class of non-volatile storage technologies that exploit the multi-level, analog tunability of ferroelectric polarization states to achieve multi-bit, history-dependent, and retention-capable memory at the device level. Unlike binary ferroelectric memories, which utilize the full reversal of spontaneous polarization, FA-NVM enables the stabilization and readout of intermediate polarization states for multi-level encoding, facilitating high-density storage, in-memory computation, and neuromorphic functionality.

1. Fundamental Principles and Device Physics

FA-NVM relies on the inherent multi-stability of the ferroelectric order parameter in materials such as Hf₀.₅Zr₀.₅O₂ (HZO), Al₀.₆₄Sc₀.₃₆N, CuInP₂S₆ (CIPS), organic ferroelectric polymers, or 2D van der Waals ferroelectrics. The system’s free energy is commonly modeled by the Landau-Ginzburg-Devonshire (LGD) framework:

$$F(P, E) = \frac{1}{2}\alpha P^2 + \frac{1}{4}\beta P^4 + \frac{1}{6}\gamma P^6 - E P$$

where $P$ is the polarization, $E$ the electric field, and $(\alpha, \beta, \gamma)$ are phenomenological coefficients. Polarization switching occurs when $E$ tilts the double-well energy landscape, with partial switching accessible via sub-coercive pulses, yielding programmable remanent polarization ($P_r$) that defines the analog storage level (Singha et al., 8 Dec 2025, Li et al., 2024, Yadav et al., 13 Nov 2025).

The macroscopic manifestation is a family of nested minor hysteresis loops in the $P$–$E$ diagram, corresponding to a continuum of accessible, stable polarization values. Experimentally, atomic- and mesoscopic-level control over domain nucleation and wall motion determines state stability, retention, and analog step precision.

Key device architectures include metal–ferroelectric–metal (MFM), metal–insulator–ferroelectric–metal (MIFM), ferroelectric field-effect transistors (FeFETs), ferroelectric tunnel junctions (FTJs), and ferroelectric/semiconductor/metal heterojunctions (Hu et al., 17 Apr 2025, Sarkar et al., 2024, Saha et al., 2020).

2. Architectures, Materials, and Integration Strategies

A wide variety of stacks and processing flows have demonstrated FA-NVM, unified by the need for high-quality, stable ferroelectric layers and robust interfaces to preserve multistate characteristics. Example devices and integration strategies include:

• HZO/WOₓ FTJ: TiN/HZO/WOₓ/TiN stacks processed at ≤375 °C (BEOL-compatible), offering >10 analog states, ON/OFF >10, and endurance >10¹⁰ cycles (Bégon-Lours et al., 2023, Bégon-Lours et al., 2023).
• Al₀.₆₄Sc₀.₃₆N FeDiode: Scaled to 50 nm diameter, achieving 8-level (3-bit/cell) retention, density >100 Mbit/mm², and increasing breakdown-to-coercive field ratio ($E_b/E_c > 2.6$) at reduced device size (Hu et al., 17 Apr 2025).
• CIPS/Graphene/In–Co van der Waals diode: 8–10 nm CIPS with graphene BE and In–Co TE showing five-level analog operation, $R_{off}/R_{on} ≈ 10^6$, endurance >10³ cycles, and complete selector-free crossbar compatibility (Sarkar et al., 2024).
• HZO Memcapacitors: MFM TiN/HZO/TiN stacks encoded for >8 analog capacitance states within a non-volatile $\Delta C ≈ 24$ pF window, >10⁶ cycles, and retention >10⁵ s, with non-destructive readout (Yadav et al., 13 Nov 2025).
• FeFETs (polymer-based): P(VDF–TrFE)/MoS₂ transistors on flexible substrates, supporting >16 distinct analog conductance states and DNN inference with >96% MNIST accuracy (Majumdar et al., 2023).

Integration with CMOS is routine in oxide-based architectures (HZO, AlScN), with sub-400 °C budgets and BEOL compatibility for both planar and 3D crossbar arrays. Two-terminal architectures (FTJ, FeDiode, memcapacitor) are favored for dense, selector-free arrays, while FeFETs enable three-terminal synapses for neuromorphic hardware (Hu et al., 17 Apr 2025, Yadav et al., 13 Nov 2025).

3. Analog Programming, Read/Write Schemes, and State Control

Multilevel memory operation is achieved by precisely modulating the electric field amplitude, pulse duration, or pulse count during programming. Key approaches:

• Incremental Voltage/Width Pulses: Applying a series of sub-coercive pulses incrementally steps the remanent polarization, exploiting the smooth nonlinearity of polarization switching (Yadav et al., 13 Nov 2025, Bégon-Lours et al., 2023).
• Partial Domain Switching: Analog levels are set by stabilizing a fraction of reversed domains, verified by piezoresponse force microscopy (PFM) and macroscopic electrical measurements (Sarkar et al., 2024, Yadav et al., 13 Nov 2025).
• Range-based Search (CAM): In FeCAM architectures, two FeFETs store lower/upper voltage bounds via analog $V_{th}$ tuning; matching occurs if the input signal lies within the programmed range. $M$ levels/device yield $M/2$ intervals for 3-bit/cell operation (Yin et al., 2020).
• Non-destructive Readout: Capacitive and resistive state readouts use small AC/DC probes ($<$0.1 V) to avoid disturbing the analog state, enabling repeated high-fidelity access (Yadav et al., 13 Nov 2025, Bégon-Lours et al., 2023).

The number of stable analog levels is determined by polarization step size, device-to-device variation, intrinsic noise, and thermal drift. Typical state counts span 5–16, corresponding to 2–4 bits/cell, with step-to-step $\sigma/\mu$ variation <10% and endurance up to $10^{10}$ cycles (Bégon-Lours et al., 2023, Li et al., 2024, Hu et al., 17 Apr 2025).

4. Performance Metrics and Benchmarking

FA-NVMs demonstrate favorable metrics compared to binary ferroelectric and alternative analog NVMs:

Device Type	Architecture	Bits/Cell	Endurance	Retention	Programming Voltage	ON/OFF Ratio	Cycle/Device $\sigma/\mu$	Area (approx.)	Ref.
HZO/WOₓ FTJ	2-terminal FTJ	>10	$>10^{10}$	$>10$ days	$\pm$1.6–2.4 V	$\sim$10	$<$10%	$~1.1\times10^4\ \mu$m²	(Bégon-Lours et al., 2023)
AlScN FeDiode	MIFM, 50 nm	8	(not reported; >$10^7$ est.)	$>5\times10^5\,$s	7.5–12 V (prog.)	up to 100 ($>$200 nm)	$<$10% state overlap	$<$1 µm²	(Hu et al., 17 Apr 2025)
CIPS vdW FeDiode	M–F–M diode	5	$>1.5\times10^3$	$>10^4$ s	2–2.5 V	$10^6$	(Not specified)	$<$1\,µm²	(Sarkar et al., 2024)
HZO memcapacitor	MFM	8	$>10^6$	$>10^5$ s	$\pm$3 V	--	$<$5% state overlap	$3600\ \mu$m²	(Yadav et al., 13 Nov 2025)
FeFET (polymer)	3-terminal FET	>16	$>10^4$	$>10^3$ s	$<$4 V	$10^4$	$<$12%	(flexible)	(Majumdar et al., 2023)

Highly scaled structures preserve retention (>5×10⁵ s), endurance ($10^6$–$10^{10}$ cycles), and state distinguishability at sub-µm nodes. Write energies are typically 1–100 pJ for capacitor-based and resistive elements, $<1$ fJ for 2D FeFETs (Singha et al., 8 Dec 2025, Yadav et al., 13 Nov 2025). Search and programming latencies of 10–100 ns are routine for compact cells (Yin et al., 2020, Hu et al., 17 Apr 2025).

5. Application Domains: Density, In-Memory and Neuromorphic Computing

Density and energy advantages position FA-NVM for several advanced roles:

• High-density Storage: Bit-per-cell metrics reach 3–4 in analog mode; FeCAM achieves $22.4\times$ density over CMOS TCAM at $0.018\,\mu$m²/bit (Yin et al., 2020). AlScN FeDiodes reach $>100$ Mbit/mm² at $4F^2$ planar scaling (Hu et al., 17 Apr 2025).
• Content-Addressable and Associative Memory: FeCAM supports digital/analog CAM with 60.5$\times$ area and 23.1$\times$ energy savings relative to CMOS CAM, with range-based analog search for pattern matching and lookup (Yin et al., 2020).
• In-memory Vector–Matrix Multiplication: Analog weighting (capacitive or resistive) enables tightly integrated VMM for neuromorphic cores. HZO memcapacitors offer in situ reconfigurability for synaptic emulation and adaptive circuit elements (Yadav et al., 13 Nov 2025, Li et al., 2024).
• 2D/Flexible Systems: Polymer/MoS₂ FeFETs and vdW FeDiodes support wearable, flexible, or ultrathin platforms (Majumdar et al., 2023, Sarkar et al., 2024).
• Analog RF Front-Ends: FA-NVM enables energy-efficient, bias-free tuning of analog/RF circuits, e.g., filters and neural front-ends (Yadav et al., 13 Nov 2025).

6. Reliability, Variability, and Trade-offs

Critical reliability attributes include cycle endurance, data retention, variability, and disturbance immunity:

• Endurance and Fatigue: HZO devices demonstrate $>10^9$ cycles with in situ recovery protocols, often leveraging high-field pulses to de-trap interface charge and restore polarization amplitude (Li et al., 2024).
• Retention: Room-temperature data retention exceeds $10^4$–$10^5$ s for most stacks and states; HZO and AlScN show minimal drift over $>10^5$ s (Yadav et al., 13 Nov 2025, Hu et al., 17 Apr 2025).
• Variability: Device-to-device variation in conductance or capacitance steps $\sigma/\mu<10\%$ is routinely demonstrated. For FeFET and FTJ arrays, crossbar-based nonlinearity facilitates suppression of sneak paths and stable inference (Bégon-Lours et al., 2023).
• Scaling Limits: Cell performance remains robust to sub-100 nm nodes; breakdown fields increase with downscaling (MIFM AlScN), but read noise may require higher pulses or reduced multibit depth (Hu et al., 17 Apr 2025).
• Trade-offs: Higher resolution (more states) demands tighter step uniformity and narrower margins, possibly limiting robustness under extreme cycling or temperature bias (Yin et al., 2020, Yadav et al., 13 Nov 2025).

Domain wall pinning, defect engineering, and interface control are key for optimizing analog precision and array-level yield. Device-specific failure modes include charge trapping, oxygen vacancy migration, and polarization fatigue.

7. Outlook and Challenges

Leading research directions include:

• Materials Innovation: Enhancement of HZO and AlScN layer uniformity, wafer-scale vdW ferroelectric synthesis, and improved defect engineering for state stability (Hu et al., 17 Apr 2025, Sarkar et al., 2024).
• BEOL and 3D Integration: Further lowering process temperatures and integrating analog ferroelectrics in advanced CMOS back end (Bégon-Lours et al., 2023, Li et al., 2024).
• Memory–Computation Convergence: Circuit-level design of compute-in-memory neuromorphic accelerators using FA-NVM as core storage–weight elements (Majumdar et al., 2023, Yadav et al., 13 Nov 2025).
• Reliability Under Scale: Maintaining cycling endurance, state separation, and read margin at nanoscale dimensions and in aggressive, high-frequency environments (Hu et al., 17 Apr 2025).
• Analog Array Control: Schemes for closed-loop calibration, training, and compensation of nonlinearities in analog weight update for stochastic and deterministic learning (Li et al., 2024).

FA-NVM has demonstrated substantial improvements in density, energy, analog functionality, and integration economics over conventional and alternative NVMs—positioning it as a central component for next-generation in-memory, neuromorphic, and mixed-signal electronic systems (Yin et al., 2020, Sarkar et al., 2024, Yadav et al., 13 Nov 2025, Bégon-Lours et al., 2023, Majumdar et al., 2023, Singha et al., 8 Dec 2025).