Reconfigurable Microwave Analog Computer (MiLAC)

• MiLAC is a reconfigurable microwave network that performs arbitrary large-scale linear algebra operations by precisely configuring lossless, reciprocal admittance networks.
• It enables energy-efficient implementations of MIMO and beamforming through analog-domain matrix–vector multiplications, reducing digital processing and RF hardware needs.
• Advanced design strategies, such as stem-connected topologies and joint optimization frameworks, facilitate scalable, high-performance analog computation in communications.

A Microwave Linear Analog Computer (MiLAC) is a reconfigurable multi-port microwave network engineered to perform arbitrary large-scale linear algebraic operations, particularly matrix–vector multiplications, directly in the analog domain by manipulating microwave signals. Operating by precise configuration of lossless, reciprocal admittance networks, MiLACs enable energy- and hardware-efficient realization of computational tasks central to communications, signal processing, and scientific computing. They provide a scalable pathway to fully analog or hybrid transmitter/receiver architectures that can match the performance of digital systems—most notably in massive and gigantic multiple-input multiple-output (MIMO)—while drastically reducing digital processing requirements, the number of RF chains, and ADC/DAC resolution demands (Nerini et al., 6 Jun 2025, Nerini et al., 18 Jun 2025, Fang et al., 5 Jan 2026, Nerini et al., 10 Apr 2025).

1. Mathematical Model and Physical Architecture

A MiLAC is constructed as an $N$-port, lossless, reciprocal microwave network, with its physical structure determined by the interconnection of tunable admittance elements (e.g., varactors, MEMS capacitors) both between pairs of ports and between ports and ground. Its internal state is characterized by an admittance matrix $\mathbf{Y} \in \mathbb{C}^{N \times N}$ with all entries purely imaginary (for losslessness) and symmetric (for reciprocity) (Nerini et al., 9 Apr 2025, Nerini et al., 6 Jun 2025, Fang et al., 5 Jan 2026):

$$\mathbf{Y} = \mathbf{B}, \quad \mathbf{B} \in \mathbb{R}^{N \times N}, \quad \mathbf{B} = \mathbf{B}^T, \quad \Im(\mathbf{B}) \neq 0.$$

The corresponding scattering (S-parameter) matrix is

$$\Theta = (\mathbf{I}_N + Z_0 \mathbf{B})^{-1} (\mathbf{I}_N - Z_0 \mathbf{B}), \quad Z_0 = Y_0^{-1}.$$

Losslessness and reciprocity impose the constraints

$$\Theta^H\Theta = \mathbf{I}_N,\quad \Theta = \Theta^T.$$

In communications applications, the ports are divided into input (“information”) ports fed by RF chains and output (“antenna”) ports attached to radiating elements. The matrix sub-block mapping the input to the output ports, typically $\mathbf{F} = \tfrac{1}{2} \Theta_{21}$, serves as the analog-domain precoder or combiner (Fang et al., 5 Jan 2026, Nerini et al., 6 Jun 2025).

2. Linear Algebraic Operations in the Analog Domain

MiLACs embed arbitrary linear operations, including but not limited to real-time matrix–vector multiplication, matrix inversion, regularized least squares, and LMMSE estimation (Nerini et al., 9 Apr 2025, Nerini et al., 10 Apr 2025). By configuring the admittance matrix, the network physically computes $v = \mathbf{Q}\tilde u$ (where $\mathbf{Q} = (\mathbf{Y}/Y_0 + \mathbf{I})^{-1}$), implementing a desired matrix transformation on the input microwave signals almost instantaneously—i.e., limited only by wave propagation delay through the network.

For instance, with proper block partition, a MiLAC can realize

$\mathbf{v}_2 = \mathbf{Q}_{21} \mathbf{u},$

where drive vector $\mathbf{u}$ encodes inputs, and $\mathbf{Q}_{21}$ is designed via admittance synthesis to realize a prescribed kernel (e.g., the Gramian inverse in LMMSE). The matrix configuration is established once per channel coherence block, with no per-symbol digital computation required (Nerini et al., 10 Apr 2025, Nerini et al., 9 Apr 2025).

3. MiLAC for Gigantic MIMO and Wireless Beamforming

MiLACs have been proposed and analyzed for massive and gigantic MIMO arrays, both at the transmitter and receiver (Nerini et al., 10 Apr 2025, Nerini et al., 6 Jun 2025). By mapping a small number $N_S$ of baseband symbol streams to $N_T \gg N_S$ antennas through a fully analog linear mapping, the MiLAC-based architecture achieves zero-forcing (ZF), regularized ZF, or MMSE beamforming with only $N_S$ RF chains, reducing hardware and computational load compared to digital architectures.

Mutual information and sum-rate analyses demonstrate that, under the ideal lossless-reciprocal MiLAC assumption, the system achieves precisely the digital MIMO channel capacity when employing optimal eigenmode transmission. For a channel $\mathbf{H} \in \mathbb{C}^{N_R \times N_T}$, the optimal MiLAC beamformer is constructed as

$$\mathbf{F}^\star = \frac{1}{2} \overline{\mathbf{V}},\quad \overline{\mathbf{V}} = [\mathbf{v}_1, \ldots, \mathbf{v}_{N_S} ],$$

where $\{\mathbf{v}_i\}$ are the first $N_S$ right singular vectors of $\mathbf{H}$. This result holds for both fully-connected and stem-connected MiLAC topologies (Nerini et al., 6 Jun 2025, Nerini et al., 18 Jun 2025).

However, in the multi-user MISO downlink, additional constraints imposed by the symmetric-unitary property of $\Theta$ generally prevent MiLAC from matching the full flexibility of digital beamforming, except in the single-user or orthogonal-user-channel limit. The optimal beamforming columns are forced to be orthogonal for maximal power transfer, leading to minor sum-rate loss except in sufficiently large arrays where channel vectors become asymptotically orthogonal (Fang et al., 5 Jan 2026, Wu et al., 15 Jan 2026).

4. Circuit Complexity, Graph Models, and Scalable Topologies

Practical realization of MiLACs is shaped by circuit complexity, dictated by the number of tunable admittances. The fully-connected topology, which interconnects each of $N = N_S + N_T$ ports to every other (plus all port-to-ground admittances), yields $O(N^2)$ tunable elements, scaling quadratically with array size (Nerini et al., 18 Jun 2025). To address this, reduced-complexity topologies, such as the "stem-connected" graph (with only $O(N_S N_T)$ components), have been proposed and rigorously shown to preserve full capacity-achieving properties.

Let $G=(V,E)$ be the underlying circuit graph, with $|V|=N$ and $|E|$ determined by the connectivity. The circuit complexity is

$N_C = N + |E|,$

where ground admittances count as node contributions and inter-port admittances as edges. Designating $Q = 2N_S-1$ center nodes in the stem-connected graph, the element count reduces to $N_S(2N_T + 1)$—enabling practical, scalable MiLAC hardware for arrays with hundreds to thousands of antennas without capacity degradation (Nerini et al., 18 Jun 2025).

5. Optimization Frameworks and Algorithmic Realization

Joint optimization of MiLAC parameters for communications involves configuring both the microwave network (scattering/admittance matrix) and high-level system variables (e.g., power allocation). The sum-rate maximization problem in the MU-MISO context is formulated as

$$\max_{\{p_k\},\,\Theta} \sum_{k=1}^{K} \log_2(1+\mathrm{SINR}_k),$$

$$\text{s.t.}\;\Theta^H\Theta = \mathbf{I},\; \Theta = \Theta^T,\; \sum_k p_k\leq P_{\text{max}},$$

where the SINR for user $k$ is

$$\mathrm{SINR}_k = \frac{p_k |\mathbf{h}_k^H \mathbf{f}_k|^2}{\sum_{i \neq k} p_i |\mathbf{h}_k^H \mathbf{f}_i|^2 + \sigma_k^2},$$

with $\mathbf{f}_k$ the $k$-th column of the beamforming matrix $\mathbf{F}$.

Due to nonconvex symmetric-unitary constraints, efficient algorithms leverage block-coordinate descent and fractional programming for variable updates, alternating between auxiliary variables, power allocation (solved via the KKT conditions), and scattering matrix synthesis (via symmetric polar decomposition). Complexity scales as $$\mathcal{O}\big(I_{\text{outer}} I_{\text{inner}} (K+L)^3\big)$$, where $(K,L)$ are the numbers of users and antennas (Fang et al., 5 Jan 2026). Similar problem structure and algorithmic techniques appear in hybrid and low-complexity WMMSE-based schemes (Wu et al., 15 Jan 2026).

6. Channel Estimation and Ancillary Computations

MiLAC-enabled architectures support efficient analog-domain implementations of least-squares (LS) and minimum mean-square error (MMSE) channel estimation. By reconfiguring the MiLAC to map training vectors optimally through analog precoders and combiners, both LS and MMSE estimators can be realized entirely in the microwave network without any online digital computation (Zhang et al., 16 Jan 2026). Key advantages include drastic reduction of required transmit RF chains (to as low as one for LS procedures), enablement of unity-peak-to-average-power-ratio (PAPR) constant-amplitude training, and utilization of low-resolution ADCs/DACs.

Performance metrics demonstrate that analog MiLAC-based estimators match the estimation error (NMSE) performance of their digital counterparts across a wide range of system dimensions and SNRs, with computational cost reductions that grow with system size—up to $2.15 \times 10^9$ flops per block saved compared to digital MMSE in $2048\times 64$ systems (Zhang et al., 16 Jan 2026).

7. Experimental Realizations, Accuracy, and Physical Constraints

Experimental and theoretical studies corroborate the feasibility, efficiency, and accuracy of MiLAC architectures (Nerini et al., 9 Apr 2025, Tzarouchis et al., 2022, Hougne et al., 2018). Experimental implementations relying on programmable metastructures, cavity-induced random mixing, and direct complex matrix (DCM) architectures have demonstrated:

• Matrix inversion, root finding (Newton’s method), and constrained optimization (Lagrange multipliers) with analog computation errors $\sim 10^{-3}$ in relative 2-norm up to $n=5$ matrix sizes (Tzarouchis et al., 2022).
• Sub-microsecond end-to-end inversion and multiplication, limited only by wave propagation and component reconfiguration times.
• Energy consumption per operation on the order of $1$ pJ/op, well below digital CMOS for similar matrix dimensions (Hougne et al., 2018).
• The main sources of performance degradation are component tolerances, calibration drift, finite $Q$ of microwave components, and nonidealities in active multiplier modules.

Scalability is currently limited by the quadratic component count for fully-connected and DCM networks, although graph-sparse topologies (e.g., stem-connected) and integration in RFIC or photonics promise improved scaling. Analog precision can be further enhanced by mixed-precision strategies, wherein coarse analog computation is refined digitally.

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References:

Key results are drawn from (Fang et al., 5 Jan 2026, Nerini et al., 18 Jun 2025, Nerini et al., 10 Apr 2025, Nerini et al., 9 Apr 2025, Nerini et al., 6 Jun 2025, Wu et al., 15 Jan 2026, Zhang et al., 16 Jan 2026, Tzarouchis et al., 2022, Hougne et al., 2018).