MiLAC-Aided MIMO Systems

• MiLAC-aided MIMO systems are analog-domain architectures that use multiport microwave networks to perform linear algebra operations like precoding and matrix inversion directly on electromagnetic signals.
• They decouple signal processing complexity and hardware costs by embedding MiLACs between few RF chains and large antenna arrays, thus enabling scalable, energy-efficient 6G and beyond implementations.
• Innovative topologies such as stem-connected MiLACs reduce circuit complexity while achieving full digital MIMO capacity, as demonstrated through SVD-based optimal designs and rigorous performance analyses.

Microwave Linear Analog Computer (MiLAC)-aided MIMO systems are a class of analog-domain architectures for multiple-input multiple-output (MIMO) wireless communications. They utilize reconfigurable, fully passive, lossless, and reciprocal multiport microwave networks—MiLACs—to perform linear algebra tasks (e.g., precoding, combining, matrix inversion) directly on analog electromagnetic waveforms. By embedding MiLACs between a small number of radio-frequency (RF) chains and large antenna arrays, these systems decouple signal processing complexity and hardware cost from the antenna array size, enabling scalable, low-power, and low-latency implementations of gigantic MIMO suitable for 6G and beyond. MiLAC architectures yield analog-domain beamforming with rigorously characterized performance and complexity benefits, and under restrictive constraints can provably achieve the full capacity of digital MIMO systems (Nerini et al., 6 Jun 2025, Nerini et al., 18 Jun 2025, Nerini et al., 10 Apr 2025).

1. Physical and Mathematical Model of MiLAC

MiLACs are multiport microwave networks, typically characterized either in admittance (Y-parameter) or scattering (S-parameter) form. For a P-port MiLAC, the admittance matrix $\mathbf{Y}$ is set via arrays of tunable impedance elements (e.g., varactors, MEMS switches). Input ports are driven by RF signals, while output ports are terminated or connected to antennas.

The key mappings are:

• Admittance formulation: For inputs $u \in \mathbb{C}^N$ and $M = P - N$ outputs:

$$v_2 = \mathbf{Q}_{21} u, \qquad \mathbf{Q} = (\mathbf{Y}/Y_0 + \mathbf{I}_P)^{-1}$$

• S-parameter (scattering) formulation: For lossless reciprocal MiLACs, the scattering matrix $\Theta$ is unitary and symmetric:

$\Theta^H \Theta = I, \quad \Theta = \Theta^T$

The desired analog precoder or combiner $F$ is implemented as a submatrix of $\frac{1}{2} \Theta$.

These constraints enforce passive (no power dissipation) and reciprocal (no non-reciprocal components) network operation, leveraging only capacitances and inductances.

2. Capacity Analysis and Optimal Beamforming in Single-User MIMO

MiLAC-aided point-to-point MIMO systems with $N_T$ transmit, $N_R$ receive antennas, and $N_S = \min\{N_T, N_R\}$ data streams use pairwise transmitter and receiver MiLACs to fully realize analog-domain beamforming. The end-to-end input–output relationship is:

$z = \sqrt{P_T} G H F P^{1/2} s + G n,$

where $F$ and $G$ are analog precoder and combiner realized by MiLAC scattering submatrices, $P = \mathrm{diag}(p_1, ..., p_{N_S})$, and $n$ is i.i.d. Gaussian noise.

Rate Maximization Problem: Finding the optimal $(F, G, P)$ subject to lossless symmetry/unitarity constraints is cast as:

$$\max_{F, G, \{p_s\}} R, \quad \text{with constraint} \quad F = \frac{1}{2} [\Theta_F]_{\text{block}},~G = \frac{1}{2} [\Theta_G]_{\text{block}}$$

The closed-form solution leverages the SVD of the channel $H = U \Sigma V^H$, yielding optimal $F^* = V_{:,1...N_S}$ and $G^* = U_{:,1...N_S}^H$, realizing SVD-based water-filling capacity. These solutions are mapped back to unitary, symmetric scattering matrices through explicit matrix completions.

Key Finding: For any rank-$N_S$ channel, MiLAC-aided beamforming achieves the same capacity as fully-digital MIMO (mutual information upper bound), i.e.,

$$C = \sum_{s=1}^{N_S} \log_2\left(1 + \frac{P_T p_s^* \sigma_s^2}{4\sigma^2}\right)$$

where $\sigma_s$ are the top singular values of $H$ (Nerini et al., 6 Jun 2025).

3. Hardware Architectures and Scalable MiLAC Design

MiLAC implementation strategies directly impact both circuit complexity and system scalability:

• Fully-Connected MiLAC: Implements any matrix subblock via all-to-all tunable admittance elements between $N_T + N_S$ (or $N_R + N_S$) ports at the transmitter (receiver). The number of tunable components scales quadratically: $O((N_T + N_S)^2)$, becoming impractical for gigantic arrays (Nerini et al., 18 Jun 2025).
• Stem-Connected MiLAC: A center-graph network topology with $Q = 2N_S - 1$ hub nodes, with leaves connected only to hubs, achieves capacity while reducing complexity to $O(N_T N_S)$ (linear in antenna count for fixed $N_S$). This architecture enables order-of-magnitude reductions in hardware for very large arrays without capacity loss (Nerini et al., 18 Jun 2025).
• Graph-Theoretic Design: The susceptance matrix $B$ is sparse per the chosen topology; design reduces to selecting weights enabling the desired SVD-based mapping via block-structured linear equations under per-edge sparsity constraints.

The table below summarizes the hardware complexity–performance trade-off:

MiLAC Topology	Achievable Capacity	Tunable Admittances (Tx/Rx)	Scaling w.r.t. $N_T$
Fully-Connected	Yes (optimal)	$O(N_T^2)$	Quadratic
Stem-Connected	Yes (optimal)	$O(N_T)$ (for const $N_S$)	Linear

4. Computational Complexity and System-Level Implications

MiLAC architectures drastically reduce computational and energy costs by shifting beamforming entirely into the analog domain:

• RF Chain Count: Reduced from $N_T$ (digital) to $N_S$ (MiLAC), achieving the information-theoretic minimum.
• ADC/DAC Resolution: MiLACs only require low-resolution conversion (2–4 bits); they carry modulated streams per RF chain, not arbitrary digital linear combinations.
• Per-Symbol Computational Load: MiLAC performs all required linear algebra (matrix multiplication, inversion) via passive microwave propagation; there are zero per-symbol digital matrix–vector multiplies, contrasting with $O(N^2– N^3)$ digital operations per symbol/block (Nerini et al., 10 Apr 2025).
• Complexity Reductions: For ZF beamforming/DMMSE detection, reductions by up to $10^4$ (ZF)–$4 \times 10^7$ (DFT) versus digital are observed for $N=8,192$. MiLAC’s complexity is dominated by $O(N^2)$ admittance settings per coherence interval, not real-time multiply-accumulates (Nerini et al., 10 Apr 2025).

Energy consumption and heat dissipation are minimized due to the elimination of massive digital signal processing and high-resolution ADC/DAC arrays (Nerini et al., 9 Apr 2025).

5. Extensions: Multi-User MISO, Hybrid Architectures, and Channel Estimation

Multi-User MISO

In the downlink MU-MISO setting (single-antenna users), MiLACs are still implemented as fully-connected analog networks interfacing a reduced number of RF chains with a larger array. However, the enforced unitary and symmetry constraints on the MiLAC’s scattering matrix mean that the set of achievable beamformers is strictly smaller than that of a fully digital system. Performance is strictly suboptimal compared to digital in the general case but becomes asymptotically optimal as the array size increases and user channels become orthogonal (Fang et al., 5 Jan 2026, Wu et al., 15 Jan 2026):

• MiLAC can match digital performance exactly only for $K=1$ or mutually orthogonal user channels.
• Hybrid digital–MiLAC architectures (where baseband processing is retained over $K$ streams and MiLAC analog beamforming is used) can recover the full flexibility of digital beamforming if the number of RF chains equals the number of streams.

Efficient alternating optimization and WMMSE-based algorithms have been proposed to jointly optimize analog network parameters and power allocation under MiLAC constraints (Wu et al., 15 Jan 2026).

Channel Estimation

MiLACs can be configured to realize training precoders and combiners for LS and MMSE channel estimation fully in the analog domain, matching digital performance but with drastically reduced computational and RF chain requirements. Analog estimation eliminates the need for digital-intensive matrix inversions, allowing for ultra-low complexity and energy usage (Zhang et al., 16 Jan 2026).

6. Practical Considerations and Implementation Challenges

• Tuning and Calibration: MiLAC performance depends on precise tuning of admittances. With available hardware (10–12 bits resolution), amplitude and phase errors below 0.1 dB and 1° are achievable, sufficient for near-capacity performance.
• Loss, Nonideality, and Scalability: Real-world varactors and passive microwave elements exhibit finite insertion loss, quality factor limitations, and tuning range constraints. Empirically, sub-dB losses have negligible impact in large arrays and can be calibrated out (Nerini et al., 18 Jun 2025).
• Robustness and Flexibility: Calibration routines, possibly aided by digital feedback, are essential for drift and mismatch correction over device lifetimes.
• RF Crosstalk and Noise: Design must ensure crosstalk between ports is matched by the designed block-matrix constraints; noise impact is minimized by the passive and lossless network design.
• Integration with Baseband DSP: While linear operations are offloaded to MiLAC, residual nonlinear, asynchronous, or lower-dimension DSP can be performed centrally, enabling a flexible analog–digital partitioning (Nerini et al., 9 Apr 2025).

7. Summary and Outlook

MiLAC-aided MIMO systems establish that fully passive, reciprocal analog networks can achieve the information-theoretic limits of digital MIMO in point-to-point links, with optimal closed-form designs for lossless architectures. In multi-user and multi-cell settings, the fundamental flexibility of MiLAC exceeds conventional phase-shifter networks but is strictly less than digital in general. Architectural innovations, such as stem-connected MiLACs, enable dramatic reductions in circuit complexity, rendering gigantic MIMO feasible with only linear scaling in hardware resources. MiLACs allow significant reductions in real-time digital processing, RF chain count, and ADC/DAC resolution without capacity loss for relevant classes of channels, and enable ultrafast, ultra-energy-efficient analog computation suitable for 6G and beyond (Nerini et al., 6 Jun 2025, Nerini et al., 18 Jun 2025, Nerini et al., 10 Apr 2025).