High Granularity Calorimeter Readout Chip (HGCROC)

• High Granularity Calorimeter Readout Chip (HGCROC) is a specialized ASIC designed for CMS HGCAL upgrades, offering precise charge and timing measurements under harsh HL-LHC conditions.
• It integrates 160 channels with dual-gain paths, a 10-bit ADC, TDC, and on-chip zero-suppression, ensuring high dynamic range and low noise performance.
• Engineered for robust radiation tolerance and low power consumption, HGCROC supports millions of channels crucial for precision calorimetry at the HL-LHC.

The High Granularity Calorimeter Readout Chip (HGCROC) is a custom front-end ASIC designed for the CMS High-Granularity Calorimeter (HGCAL) upgrade, targeting operation in the extreme radiation and pile-up conditions of the HL-LHC. HGCROC serves as the principal interface between silicon pad sensors (0.5–1 cm²) and scintillator tiles coupled to silicon photomultipliers (SiPMs), enabling precision pulse-height and time-of-arrival measurements across a large dynamic range while maintaining stringent power and radiation tolerance constraints (Quast, 2021).

1. Functional Architecture

Each HGCROC integrates 160 independent readout channels, each comprising a charge-sensitive preamplifier (CSA), dual-gain CR–RC² shaping amplifiers, discriminators with time-over-threshold (TOT) logic, a 10-bit Wilkinson ADC, a 10-bit time-to-digital converter (TDC), programmable digital logic, and high-speed serializers. The analog front end features separate high- and low-gain paths: the high-gain output feeds the ADC with an input dynamic range up to 50 fC (around 50 MIPs), while the low-gain path enables TOT measurements for signals up to 2 pC (about 2000 MIPs). Sensor interconnections use bump-bonding (silicon pads) or wire-bonding (SiPM tiles).

The architecture includes in-chip programmable thresholds, zero-suppression, multi-level buffering, and two independent high-speed output links—one for the data path (ECON-D) and one for triggering (ECON-T).

2. Analog and Digital Signal Processing

The CSA provides initial charge amplification, followed by a semi-Gaussian CR–RC² shaper with adjustable peaking time in the range $\tau_p \approx 50$–$100\, \mathrm{ns}$. The shaper transfer function is specified as:

$$H(j\omega) = \frac{(j\omega \tau_p)}{(1 + j\omega \tau_p)^3}$$

Signal discrimination and timing are implemented via a leading-edge discriminator and a per-channel 10-bit TDC, achieving binning of 25 ps with a 40 MHz reference clock and a measurement range up to 25.6 ns per L1 accept window. Charge digitization utilizes a 10-bit Wilkinson ADC, with conversion time constrained to be less than the signal peaking time (to support 40 MHz sampling). Hit parameters (TOT, ADC, TDC words) are formatted and forwarded for further zero-suppression in the data aggregator.

3. Key Specifications

HGCROC was engineered to meet the following critical specifications, as demonstrated in simulations and prototype testing:

• 160 channels per chip, supporting a final system granularity of approximately 6 million channels.
• Input dynamic range: 0–50 fC in high-gain ADC path, 0–2 pC in low-gain TOT path.
• ADC resolution: 10 bits (INL < 1%, DNL < 0.5 LSB).
• TDC resolution: 25 ps per LSB, enabling 10-bit time stamps.
• Shaper peaking time: typically 60 ns, tunable within 50–100 ns.
• Noise performance: equivalent noise charge (ENC) $\approx$ 1000–1500 $e^-$.
• Time resolution: design target $\leq 50$ ps (measured 70 ps in prototype for 250 GeV $e^\pm$).
• Channel-to-channel cross-talk: $<0.3\%$ (measured).
• Power consumption: $\leq 20\,\mathrm{mW}$/channel (3.2 W per chip).

Calibration is supported by an on-chip charge injection DAC, permitting gain and timing verification with both internal pulses and externally provided MIP signals.

Parameter	Specification / Target	Prototype Measurement
Channels / Chip	160	–
Dynamic Range (HG)	0–50 fC	–
Dynamic Range (LG)	0–2 pC	–
ADC Resolution	10 bit	DNL < 0.5 LSB, INL < 1%
TDC Resolution	25 ps/LSB (10 bit)	≤30 ps
Peaking Time	50–100 ns	60 ns
Noise (ENC)	≤1500 $e^-$	$\sim$1000 $e^-$
Time Resolution	≤50 ps	70 ps (prototype)
Cross-Talk	<1%	<0.3%
Power / Channel	≤20 mW	20 mW

4. Power Management and Integration

Total channel power is rigorously constrained to $P_{\text{ch}}\leq 20\,\mathrm{mW}$, enabling large-scale integration (6 million channels) without excessive thermal load. Power allocation per function: CSA & shaper (8 mW), discriminator & TOT (3 mW), ADC (4 mW), TDC and digital logic (5 mW). The typical total chip dissipation with 160 channels is about 3.2 W, including I/O and bias circuits. This level of integration and power control enables the HGCROC to meet the calorimeter’s compactness and thermal requirements at HL-LHC.

5. Radiation Tolerance

To operate reliably in the HL-LHC endcap environment, HGCROC must withstand at least 100 Mrad total ionizing dose (TID) and non-ionizing energy loss (NIEL) above $1 \times 10^{16}\, \mathrm{n_{eq}/cm^2}$. The design uses 65 nm CMOS with radiation-hard libraries. Single-event upset (SEU) sensitivity is mitigated via triple-redundant configuration registers and error-correcting codes. Radiation qualification is ongoing to validate TID and SEU robustness for production deployment (Quast, 2021).

6. Performance Metrics

Post-layout simulations indicate time resolution $\sigma_t \approx 30$–$40\,\mathrm{ps}$ for $Q \geq 1$ MIP, with prototype beam test measurements (using CALICE electronics) yielding $\sigma_t \approx 70\,\mathrm{ps}$ for 250 GeV $e^\pm$. Linearity (integral non-linearity $<1\%$), differential non-linearity ($<0.5$ LSB), and channel-to-channel cross-talk ($<0.3\%$) are all within design goals. The theoretical timing resolution following CR–RC² shaping, assuming white voltage noise $N_0$ and signal slew rate $S$, is:

$$\sigma_t \approx \frac{1}{\text{SNR}}\frac{\tau_p}{\sqrt{12}},$$

where SNR is the ratio $Q_\text{signal}/Q_\text{noise}$. The measured noise performance (ENC) is approximately 1000–1500 $e^-$. Integrated zero-suppression enables efficient data handling, maintaining trigger fidelity while minimizing data volume.

7. Calibration and Operation

On-chip calibration employs an integrated charge-injection DAC to enable gain and timing adjustment per channel, supplementing regular in-situ calibrations from injected pulses and minimum-ionizing particle (MIP) signals traversing the detector. Programmable discriminator thresholds and fine time-binning support HGCAL’s combined requirements for charge and timing precision. These features, combined with the digital back end's ability to package hit parameters for downstream data compression and selection at the trigger level, are critical for sustaining HL-LHC data rates and experimental precision.

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HGCROC demonstrates successful integration of low-noise analog signal processing, high-density high-speed digitization, on-chip zero-suppression, and robust digital control, all within a radiation-tolerant sub-20 mW/channel budget to meet the CMS HGCAL’s high-precision, high-rate, and high-radiation requirements (Quast, 2021). Ongoing qualification and mass production readiness will validate its operational robustness for the HL-LHC era.