CMS Endcap Timing Layer (ETL)

• ETL is a high-precision 4D tracking subsystem using LGAD sensors to achieve 30–50 ps per-hit timing resolution in extreme high-luminosity conditions.
• It integrates thin LGAD matrices with the ETROC ASIC for effective pileup mitigation, offering fine spatial segmentation and robust radiation hardness.
• On-chip automatic calibration and radiation-tolerant electronics enable fast, reliable performance critical for CMS event reconstruction and vertexing.

The Endcap Timing Layer (ETL) is a dedicated high-precision tracking and timing subsystem in modern collider experiments, designed to provide per-hit time measurements with tens of picoseconds resolution, essential for effective pileup mitigation and advanced event reconstruction in extreme high-luminosity environments. The term typically refers to the system as implemented for the CMS Phase-II upgrade at the High-Luminosity LHC (HL-LHC), though similar concepts exist in other large-scale spectrometers. The canonical ETL implementation is based on thin Low-Gain Avalanche Detector (LGAD) arrays, bump-bonded to custom readout ASICs—most notably the Endcap Timing Layer ReadOut Chip (ETROC)—to realize a 4D pixelated detector with sub-50 ps single-hit timing, high occupancy tolerance, and robust radiation hardness (Palluotto, 18 Jan 2026, Huang et al., 2024, Dutta, 2018, Sun et al., 2021).

1. System Architecture and Physics Motivation

The ETL is geometrically composed of two circular disks per endcap, installed between the tracker and electromagnetic calorimeter (ECAL) at $|z| \approx 3.2$–3.8 m, covering the pseudorapidity range $1.6 < |\eta| < 3.0$. Each disk comprises modular hybrids integrating $16 \times 16$ LGAD matrices (pitch $1.3\,{\rm mm}$), for a total ETL instrumented area of $\approx14\,{\rm m}^2$ and $\sim8×10^6$ independent electronic channels (Palluotto, 18 Jan 2026, Huang et al., 2024). The ETL functions as a 4D tracker layer, providing a precise time stamp for every charged particle hit crossing the endcap region. This enables time tagging of minimum-ionizing particles with initial per-hit resolution $\sigma_t\sim30$–$40$ ps, degrading to $<50$ ps at end-of-life dose.

The physics impetus for the ETL arises from the HL-LHC environment, which produces $\langle \mu \rangle \sim200$ pileup interactions per bunch crossing. The spatial and temporal distribution of collision vertices results in $O(10\,{\rm cm})$ spread along $z$ and $O(200\,{\rm ps})$ in $t$. By measuring track timestamps with 30–50 ps resolution, the ETL enables 4D vertexing, improving track-vertex association, reducing fake objects from pileup, and enhancing reconstruction in multi-object and rare-process searches (Palluotto, 18 Jan 2026, Dutta, 2018, White, 2014).

2. Sensor Technology and Segmentation

The ETL employs thin ($d=50\,\mu$m) n-in-p LGADs as its fundamental sensing technology, chosen for their combination of fast signal development, internal gain ($G \sim 10$–$30$), and radiation tolerance up to $1.6\times10^{15}\,\rm n_{eq}/cm^2$ (Palluotto, 18 Jan 2026, Dutta, 2018, Sun et al., 2020). Each LGAD pad (cell) is $1.3\times1.3\,\rm mm^2$, producing a charge $\sim 15\,\rm fC$ for a minimum-ionizing particle. The gain layer is engineered with shallow p$^+$ implants, with co-implanted carbon to suppress acceptor removal and maintain gain under irradiation.

Each disc is tiled with LGAD matrices, where a module comprises four $16\times16$ arrays and associated ETROC (Palluotto, 18 Jan 2026, Huang et al., 2024). The sensor capacitance per pad is $C_s\approx2\,\rm pF$. By ensuring small pad size, the occupancy per bunch crossing at HL-LHC intensities is maintained at $<1\%$ per channel. The thin active region ensures minimal Landau fluctuations (timing spread $\sim 25$ ps) and fast charge collection (rise time $\sim 500$ ps).

3. Readout Electronics: ETROC and Per-Pixel Chain

Each LGAD pad is bump-bonded to one channel of the ETROC ASIC, implemented in 65 nm CMOS (Huang et al., 2024, Sun et al., 2020, Sun et al., 2021). The per-pixel chain consists of:

• Preamplifier: Buffered transimpedance amplifier with programmable feedback to match LGAD rise time and optimize signal-to-noise. Simulated and measured ENC $<1.4\,e^-$, power $0.74$–$1.55\,\rm mW$/pixel depending on mode (Sun et al., 2020, Sun et al., 2021).
• Discriminator: Leading-edge threshold discriminator (DAC programmable, 10 bit, 0.4 mV step), with programmable hysteresis and on-chip RC filtering for stability (Sun et al., 2020, Sun et al., 2021).
• Time-to-Digital Converter (TDC): Single delay-line architecture (no DLL), measuring both Time-of-Arrival (TOA) and Time-over-Threshold (TOT) with double-strobe self-calibration for process, voltage, and temperature tracking. Achieves TOA bin size $17.8\,\rm ps$, precision $5.6\,\rm ps$ after INL correction, and power consumption $<200\,\mu\rm W$/pixel at 1% occupancy (Zhang et al., 2020, Huang et al., 2024).
• Calibration Logic: Fully-automatic in-pixel threshold calibration, using a sample-accumulation and binary successive approximation algorithm. Entire array calibrates in parallel with 35 ms per-chip latency, dynamic power $300\,\mu$W/pixel only during calibration. The circuit is protected by Triple Modular Redundancy (TMR) for radiation hardness (Sun et al., 2021).

All electronics are designed to tolerate $\gtrsim$100\,Mrad Total Ionizing Dose (TID) and mitigate Single Event Effects (SEE) via hardened layouts and redundant logic (Sun et al., 2021, Sun et al., 2021).

4. Timing Performance and Calibration

The ETL’s timing resolution is determined by the convolution of LGAD sensor jitter, preamplifier/discriminator noise, and TDC quantization error. The per-hit time resolution is given by

$$\sigma_{\rm total}^2 = \sigma_{\rm sensor}^2 + \sigma_{\rm preamp}^2 + \sigma_{\rm disc}^2 + \sigma_{\rm TDC}^2 + \sigma_{\rm walk}^2,$$

with typical operational values $\sigma_{\rm sensor}\sim20$ ps, $\sigma_{\rm preamp}\sim10$ ps, $\sigma_{\rm disc}\sim5$ ps, $\sigma_{\rm TDC}\sim6$ ps. TOT-based time-walk correction, based on polynomial parameterization of TOA vs. TOT per channel, brings residual walk to $<5$ ps (Huang et al., 2024, Sun et al., 2020, Sun et al., 2021).

Beam test and system-level measurements consistently report single-hit timing resolutions of $30$–$40$ ps at full bias and $<50$ ps after irradiation, with efficiency $>99\%$ for MIPs. Two-layer (“track-level”) resolutions reach $30$–$35$ ps (Huang et al., 2024, Palluotto, 18 Jan 2026).

In-pixel calibration enables baseline and threshold tracking with $<1$ s total cycle. This is orders of magnitude faster than traditional off-chip S-curve scans, which require charge injection and slow control and take $O(1)$ hour per detector (Sun et al., 2021). Radiation hardness of timing is demonstrated up to $1.6 \times 10^{15}\,{\rm n_{eq}/cm^2}$ fluence.

5. Integration, Data Acquisition, and System-Level Considerations

ETL modules are mounted on carbon-fiber support disks, cooled by two-phase CO$_2$ to maintain sensor temperature ($T\sim -20^\circ$C) for leakage current and radiation tolerance. Each module’s data is serialized (1.28\,Gbps) and transmitted optically to off-detector electronics, merging into the global CMS Phase-II DAQ via lpGBT protocols (Zhang et al., 2023, Dutta, 2018).

The ETROC’s on-chip Phase-Locked Loop (PLL) delivers all necessary clocks (40\,MHz, 320\,MHz, 1.28\,GHz, 2.56\,GHz) with $<$2 ps RMS jitter and is radiation-hardened via TMR and automatic frequency calibration (AFC) (Sun et al., 2021). The DAQ system supports per-channel rates consistent with $1\%$ hit occupancy (corresponding to HL-LHC pileup).

Modules are calibrated and monitored in situ, using a combination of laser synchronization, bias/DAC scans, and periodic slow-control commands. Uniformity across the $10^4$–$10^5$ channel scale is ensured by on-board redundancy (TMR) and distributed clock architecture. Total power consumption per ETROC2 chip is $<1$ W ($<4$ mW/channel), in line with cooling requirements (Huang et al., 2024, Palluotto, 18 Jan 2026).

6. Comparative Context: ETL vs. Other Timing Layers

The ETL design has informed and guided similar upgrades in other detectors. For instance, the BESIII Endcap Time-Of-Flight system employed large-area plastic scintillators but migrated to thin, segmented MRPCs to achieve improved multi-hit rejection and sub-60 ps timing (Zhang et al., 2012, Ping et al., 2013). In the CMS ETL, the use of LGADs enables finer spatial segmentation ($1.3\,{\rm mm}$ vs. $\sim10$ mm) and higher granularity while achieving system-level power, latency, and robustness demanded by LHC conditions.

Design studies comparing technologies—LGADs, deep-depleted APDs, and MicroMegas “gas-PMT” detectors—repeatedly selected LGADs for the best balance of timing, radiation hardness, and integration with per-pixel ASIC readout (White, 2014).

The ETL’s on-chip calibration approaches reduce downtime by factors $>10^3$ compared to off-chip, manual S-curve or laser-scanned procedures (Sun et al., 2021). The use of delay-line TDCs (not DLL-locked) with self-calibration enables sub-10 ps digital resolution at low power density (Zhang et al., 2020, Huang et al., 2024).

7. Outlook and Production Status

System prototypes have met all key requirements for performance, efficiency, and radiation tolerance. Production and assembly are scheduled at four major centers, with module production starting in late 2025 and installation planned for 2028–2029 (Palluotto, 18 Jan 2026). Key challenges include ensuring timing calibration stability ($<10$ ps drift), gain layer stability under long-term irradiation, and scaling QA throughput for $>8000$ modules.

Once operational, the ETL will deliver full 4D vertexing capability in the CMS endcaps, substantially mitigating pileup and enhancing sensitivity in diverse physics channels. Current R&D efforts target further integration of clock distribution, serial readout, and memory-gated noise suppression for the forthcoming ETROC2 and future timing upgrades (Huang et al., 2024).

---

References:

• (Palluotto, 18 Jan 2026): "Precision timing at the HL-LHC with the CMS MIP Timing Detector: current progress on validation and production"
• (Huang et al., 2024): "ETROC1: The First Full Chain Precision Timing Prototype ASIC for CMS MTD Endcap Timing Layer Upgrade"
• (Sun et al., 2021): "In-pixel automatic threshold calibration for the CMS Endcap Timing Layer readout chip"
• (Sun et al., 2020): "The Analog Front-end for the LGAD Based Precision Timing Application in CMS ETL"
• (Sun et al., 2021): "Characterization of the CMS Endcap Timing Layer readout chip prototype with charge injection"
• (Zhang et al., 2020): "A Low-Power Time-to-Digital Converter for the CMS Endcap Timing Layer (ETL) Upgrade"
• (Sun et al., 2021): "A radiation tolerant clock generator for the CMS Endcap Timing Layer readout chip"
• (Dutta, 2018): "Precision Timing with the CMS MIP detector"
• (Zhang et al., 2023): "An FPGA-based readout chip emulator for the CMS ETL detector upgrade"
• (Zhang et al., 2012): "A GEANT4 Simulation Studyof BESIII endcap TOF Upgrade"
• (Ping et al., 2013): "Prototype of time digitizing system for BESIII endcap TOF upgrade"
• (White, 2014): "R&D for a Dedicated Fast Timing Layer in the CMS Endcap Upgrade"