Petiroc 2A ASICs for RICH Detector Readout

• Petiroc 2A ASICs are 32-channel front-end devices that integrate charge amplification, semi-Gaussian shaping, and dual TDC for precise timing and charge measurements.
• They achieve sub-100 ps timing resolution and high photon detection efficiency through fine calibration, noise optimization, and dual-stage time-to-digital conversion.
• Deployed in ALICE 3 RICH prototypes, these ASICs enable effective single-photon discrimination and high-precision angular resolution under challenging beam-test conditions.

The Petiroc 2A is a 32-channel front-end application-specific integrated circuit (ASIC) designed for fast, low-noise photodetector readout, with simultaneous charge and timing capabilities. Its deployment in the context of silicon photomultiplier (SiPM)-based Ring Imaging Cherenkov (RICH) detectors for the ALICE 3 experiment at the CERN LHC is distinguished by its sub-100 picosecond time resolution and robust per-channel calibration methodologies. The Petiroc 2A ASIC forms the backbone of the readout system for both aerogel proximity-focusing RICH and time-of-flight charged particle discrimination in the most recent ALICE 3 barrel RICH prototypes, where it has been validated at the system level in test-beam campaigns (Mazziotta et al., 18 Jan 2026, &&&1&&&).

1. Internal Architecture and Functional Overview

The Petiroc 2A ASIC integrates 32 independent channels, each AC-coupled to an external photosensor such as a SiPM microcell or group thereof. Each channel comprises a low-noise charge amplifier and semi-Gaussian shaper directly feeding a Wilkinson architecture 10-bit ADC for pulse-height (charge) digitization. Timing information is acquired by a fast leading-edge discriminator, which simultaneously triggers the ADC integration and enables a dual-stage time-to-digital conversion (TDC) process. The TDC incorporates:

• Coarse time (CT): A 9-bit counter clocked at 40 MHz (25 ns period, $P_{40}$).
• Fine time (FT): An on-chip time-to-amplitude converter (TAC) sampled by a 10-bit counter, yielding a nominal least significant bit (LSB) of 37 ps.

On-chip digital registers enable programming of channel-specific thresholds, discriminator polarity, and operational modes by an external controller (typically a Kintex-7 FPGA), which also orchestrates slow control, trigger distribution, and readout (Altamura et al., 18 Jan 2026).

2. Electrical Performance and Calibration Protocols

System-level deployment in the ALICE 3 bRICH detector emphasizes several electrical parameters and associated calibration steps:

Parameter	Value/Setting	Context
Channels per ASIC	32	All readouts (ring and timing arrays)
TDC bin size (LSB)	37 ps	Determined by FT ramp, per chip calibration required
ADC resolution	10 bits	PE-resolved single-photon charge measurement
Typical threshold for ring arrays	0.5–1 PE	Channel-by-channel optimized against dark count
Typical threshold for timing array	3–4 PE	Reduced noise, maintains multi-PE detection
DAQ acquisition window	550 ns per trigger	Set by FPGA, matches shaper integration window

Charge measurement calibration consists of offline pedestal subtraction (per-channel) and identification of single-photoelectron peaks to map ADC counts to PE, enabling integer photoelectron discrimination. Timing calibration requires two steps: (a) correction of per-channel static offsets due to cable, route, and time-of-flight differences (with reference planes such as fiber trackers or dedicated SiPM channels), and (b) time-walk correction as a function of detected charge, typically implemented via lookup tables or parametric fits for $\Delta t$ vs. Npe (Mazziotta et al., 18 Jan 2026).

The absolute timestamp $t$ in ns is reconstructed as:

$$t(\text{ns}) = P_{40} \times \left[ \text{CT} + 1 - \frac{ (\text{FT} - \text{FT}_{\min}) }{ (\text{FT}_{\max} - \text{FT}_{\min}) } \right]$$

with $P_{40}=25$ ns, and FT running from approximately 300 to 1000 DAC units (Altamura et al., 18 Jan 2026).

3. Noise Performance and Timing Resolution

The combined system (SiPM + Petiroc 2A) achieves sub-nanosecond timing performance under realistic beam-test conditions:

• For single-photon hits (1 PE), the relative time-difference distribution between ring array photon candidates and track time exhibits a standard deviation $\sigma \approx 400$ ps. This width is dominated by Petiroc 2A channel jitter rather than the intrinsic SiPM transit-time spread.
• For multi-PE clusters in the central timing array, the system achieves $\sigma_{\text{total}} \lesssim 100$ ps, with relative timing between separate SiPM arrays (each read out via Petiroc 2A) reaching $\sigma \approx 75$ ps for clusters with $\geq 30$ PE. Subtracting contributions in quadrature yields a single-channel timing resolution of approximately 50 ps (Mazziotta et al., 18 Jan 2026, Altamura et al., 18 Jan 2026).

Background noise, including dark counts and uncorrelated electronics noise, is effectively suppressed by tight ($\pm 5$ ns) time-window cuts, reducing uncorrelated background fraction in signal regions from 45% to below 8% with $> 95\%$ detection efficiency for valid hits (Altamura et al., 18 Jan 2026).

A general form for the timing jitter budget, though not explicitly decomposed in the source, is

$$\sigma_t = \sqrt{ \sigma_{\text{electronic}}^2 + \sigma_{\text{SiPM}}^2 }$$

4. Detector Integration and Data Acquisition

In the tested RICH prototypes, Petiroc 2A is physically integrated on custom front-end boards that also carry SiPM high-voltage bias modules (CAEN A7585D) and Kintex-7 FPGAs for slow control and fast data acquisition. Each front-end board supports four Petiroc 2A ASICs. Signal flow employs 1 m, 50 Ω controlled-impedance Samtec cables, with SiPM carrier boards routing sensor outputs via multi-channel connectors to the Petiroc-equipped DAQ boards.

Thresholds are programmed per channel based on offline calibration and are set to optimize the balance between single-photon detection efficiency and noise rejection, with typical parameterization lying just above pedestal for ring arrays and between PE peaks in the timing array. The system uses a 550 ns acquisition window per external trigger, matched to the Petiroc shaper integration time (Altamura et al., 18 Jan 2026).

Thermal management for SiPMs—including mounting on copper plates cooled via Peltier cells and CO₂ heat pipes—is maintained between –5 °C and 0 °C, depending on array position (Altamura et al., 18 Jan 2026).

5. System-Level Performance in RICH Prototypes

Application of the Petiroc 2A ASIC in test-beam campaigns with ALICE 3 RICH prototypes demonstrates its suitability for high-precision photon and timing measurements:

• Single-photon angular resolution: $\sigma_c \approx 3.8$ mrad at the Cherenkov angle saturation point ($\theta_c \approx 242$ mrad) for 10 GeV/c pions. This is independent of beam momentum within statistical uncertainties (Altamura et al., 18 Jan 2026).
• Cluster-level (multi-PE) relative time resolution: $\sigma \approx 75$ ps for $N_{\text{PE}} \geq 30$.
• Photon-counting efficiency: Exceeds 98% for clusters of $\geq 15$ PE.
• Ring-averaged angular resolution extrapolates as $\sigma_{\text{ring}} < 1.5$ mrad for $N_{\text{ph}}>6$ over limited ring coverage, scaling as $1/\sqrt{N_{\text{ph}}}$ (Altamura et al., 18 Jan 2026).

Correlated backgrounds from Rayleigh-scattered and secondary photons are synchronous in time and not removed by time matching, but remain subdominant ($\sim 0.4$ hits/track in a $\pm 5$ ns window). The Petiroc 2A-based system thus meets or surpasses the anticipated ALICE 3 RICH requirements for single-photon sensitivity, angular and temporal resolution, and background suppression (Mazziotta et al., 18 Jan 2026, Altamura et al., 18 Jan 2026).

6. Data Analysis and Calibration Strategies

Analysis of Petiroc 2A data involves several key steps:

1. Pedestal subtraction: Extraction and subtraction of ADC pedestals channel-by-channel to obtain net charge.
2. ADC$\rightarrow$PE calibration: Identification of discrete photoelectron peaks in charge spectra to convert ADC values to a physical PE scale.
3. Time-alignment: Use of external references (T0 fiber tracker or selected SiPM channels) to correct per-channel offsets.
4. Time-walk correction: Application of lookup tables or analytic fits to compensate the pulse-height dependence of leading-edge discriminator timing.
5. Threshold optimization: Iterative adjustment based on balancing signal efficiency and background rejection, implemented via programmable ASIC registers.

These steps are essential for realizing the fundamental charge and timing resolution of the Petiroc 2A in demanding time-of-flight and photon-imaging RICH applications.

7. Limitations and Open Technical Details

The internal architectural details of the Petiroc 2A ASIC—such as pole-zero network structure of preamplifiers, specific discriminator and shaping parameters, input dynamic range, and detailed power consumption per channel—are not provided in the cited test-beam publications. No explicit formulae for the Petiroc 2A pulse shaping or breakdown of timing jitter contributions are documented in the data; performance figures are presented at the integrated system level, and calibration procedures are described in terms of channel-level correction algorithms and lookup table application (Mazziotta et al., 18 Jan 2026, Altamura et al., 18 Jan 2026).

This suggests that full optimization or modeling of Petiroc 2A channels in differing detector contexts must rely on supplemental device-level characterization or direct consultation of manufacturer datasheets.

• "Development of a novel compact and fast SiPM-based RICH detector for the future ALICE 3 PID system at LHC" (Mazziotta et al., 18 Jan 2026)
• "Beam test studies for a SiPM-based RICH detector prototype for the future ALICE~3 experiment" (Altamura et al., 18 Jan 2026)